The present invention relates to a method of manufacturing a silicon epitaxial wafer, used as a substrate for circuit devices such as LSI (large scale integrated circuit), having a silicon epitaxial film formed thereon, and more particularly, to a method of manufacturing a silicon epitaxial wafer to exhibit sufficient gettering capability from the initial stage of device manufacturing process by heat treatment under predetermined condition after epitaxial growth treatment.
As the high integration trend of silicon semiconductor integrated circuit devices has been rapidly progressed, a silicon wafer from which devices are formed is subjected to increasingly severe specifications. In a device active region of the highly integrated devices, since the existence of crystal defects or metal impurities other than a dopant increases leakage current in the P/N junction or degrade gate oxide film characteristics of MOS devices, the crystal defects or the metal impurities is subject to more rigorous limitation than before.
Conventionally, a wafer produced by slicing a silicon single crystal obtained through the Czochralski method has been used for highly integrated devices. Generally, this wafer contains over-saturated interstitial oxygen at a concentration of 10-18xc3x971017 atoms/cm3. Although oxygen is effective for enhancing the strength of a wafer by preventing generation of dislocation or for providing gettering effect, oxygen is well known to deposit in the form of an oxide and to induce crystal defects such as dislocations or stacking faults due to heat histories during production of a device.
The oxide precipitates and the crystal defects generated within a wafer sufficiently away from the device active region are allowed to enjoy the function of intrinsic gettering (hereinafter referred to as xe2x80x9cIGxe2x80x9d) having the effect of gettering metal contamination. Therefore, it is understood that in order to manufacture a high yield device, the existence of the oxide precipitates or the crystal defects within a wafer is indispensable. Hereinafter, the ability that a silicon wafer exhibits IG function is called xe2x80x9cIG capabilityxe2x80x9d.
The inventors suggested the IG capability evaluation method even taking micro-oxide-precipitates that were hard to be observed in the past into consideration. This IG capability evaluation method is based on the calculation result from the size distribution of oxide precipitates by a calculator simulation using Fokker-Planck equation (refer to Japanese Patent Application No. 10-236662). Specifically, this method is to evaluate whether the following equation (b) is satisfied or not,
Lxc3x97D0.6xe2x89xa71.0xc3x97107xe2x80x83xe2x80x83(b)
wherein L(nm) is the diagonal length of oxide precipitates, and D(/cm3) is the precipitate density. If the above equation is satisfied, the excellent IG capability can be obtained.
On the other hand, a DZ (denuded zone) layer which is free of crystal defects and which has a thickness of about tens of (xcexcm is formed near the wafer surface by diffusion of oxygen to the outside, since the wafer is heat-treated at a high temperature of 1,100-1,200xc2x0 C. for several hours in so-called device active region near the wafer surface so as to form a field oxide film through LOCOS (local oxidation of silicon) or well diffusion layer. The DZ layer serves as a device active region, thereby providing a reduction in crystal defects.
However, according to higher density of integration, a high-energy ion implantation method has been used to form well diffusion layer, and when the device process is carried out at a lower temperature than 1,000xc2x0 C. in order to manufacture device with shallower junction depth, oxygen is not diffused sufficiently, and thus, the DZ layer is not formed satisfyingly. With this reason, it has become difficult to suppress crystal defects in the device active region.
Accordingly, the oxygen concentration of the substrate was reduced, but the result was unsatisfactory since the crystal defects could not be suppressed sufficiently, and the performance of the wafer was deteriorated by oxygen reduction. Therefore, an epitaxial wafer on which Si epitaxial layer including few crystal defects on the silicon slice to be wafer substrate was grown has been developed and has been used in highly integrated devices.
However, since a high temperature treatment of 1,050-1,200xc2x0 C. is applied to the process of forming an epitaxial layer on the surface of the wafer, the oxide precipitation within the wafer is significantly suppressed during continuing device process. This phenomenon was reported that in usual cases except for the case of a wafer with a high doping concentration of boron (for example, the case of a resistivity  less than 20 m xcexa9cm), it became remarkable, and thus, gettering effect for metal contamination could not be expected (S. Sadamitsu et al., Solid State Phenomena Vol. 57-58 (1997) p. 53-62).
As described in the above, when an epitaxial wafer is adopted for a highly integrated device, gettering effect for metal contamination by a high temperature treatment during epitaxial growth treatment cannot be expected. As a consequence, a silicon single crystal doped with a nitrogen concentration of at least 1013 atoms/cm3 was suggested for a substrate of an epitaxial wafer (for example, Japanese Patent Laid-Open No. 11-189493).
When the suggested silicon single crystal is used, in case of an epitaxial wafer which was sliced from the above silicon single crystal and conducted with film-forming on the surface, the oxide precipitates can exist in a density of about 108/cm3 at a previous step before the device process because the oxygen doped during crystal-producing step can serve to promote oxide precipitation. Further, those oxide precipitates grow in accordance with the device process, and form sufficient density and size for gettering, for example, thereby satisfying the above equation (b). Therefore, when the suggested silicon single crystal is used, an epitaxial wafer with the excellent IG capability can be obtained in accordance with the device process.
However, even if an epitaxial wafer is sliced from a silicon single crystal doped with nitrogen, it is difficult to obtain an epitaxial wafer with the density and the size of the oxide precipitates satisfying the above equation (b) before the device process. With this reason, there is a problem that it is easily influenced by metal contamination because it is difficult to obtain the sufficient IG capability in the initial stage of the device process.
With the foregoing insufficient IG capability problem in the initial stage of the device process in the above-described epitaxial wafer in view, the present invention is aimed at to provide a method of manufacturing a silicon epitaxial wafer, used as a semiconductor device, containing oxide precipitates with density and size sufficient for gettering from the previous step of the device process.
In other words, in the case of an epitaxial wafer treated from a silicon wafer without nitrogen doping, the density of the oxide precipitate nuclei for forming precipitates may be deteriorated or exterminated because of a high temperature treatment during epitaxial growth treatment. With this reason, generally, in the case of IG treatment for an epitaxial wafer, two-step annealing is adopted since a high temperature heat treatment is needed to form oxide precipitates by growing the oxide precipitate nuclei after a low temperature heat treatment (about 700xc2x0 C.) for several hours to induce the oxide precipitate nuclei within the wafer.
On the other hand, in case of an epitaxial wafer treated from a substrate doped with nitrogen, oxide precipitates can exist by means of the nitrogen function to induce oxide precipitates in the previous step before the device process. However, although the sufficient IG capability is possible according to the device process, excellent IG capability cannot be expected in the initial stage since the density and the size of the oxide precipitates are insufficient.
As described above, the inventors suggested the following equation to evaluate whether the following equation is satisfied or not,
Lxc3x97D0.6xe2x89xa71.0xc3x97107xe2x80x83xe2x80x83(b)
wherein L(nm) is the diagonal length of the oxide precipitates, and D(/cm3) is the density of precipitation.
This evaluation method does not need a manufacturing MOS device that is used for the evaluation of gate oxide integrity, and can be conducted in shorter time than conventional evaluation method to measure the electric characteristics such as gate oxide integrity.
Also, it is understood that if the applied range of density and size of the oxide precipitates with a predetermined IG capability is secured, reproduction can be secured at later evaluation. Therefore, if the above-mentioned evaluation using the above equation (b) is applied, it is easy to evaluate the IG capability before starting the device process.
FIG. 1 shows the relation between the density and size (diagonal length) of the oxide precipitates in an example of the present invention and comparative examples that will be described later. The IG capability in the example satisfying the above equation (b) is excellent, and the IG capability in the comparative example unsatisfying the above equation (b) is not shown. Like this, the IG capability in an epitaxial wafer can be determined by evaluating whether the above equation (b) is satisfied or not.
Accordingly, with the above evaluation method, the inventors have developed an epitaxial wafer that can exhibit the IG capability before starting the device process. Specifically, a study was conducted to determine the kind of atom to be doped into silicon single crystal, and to specify the doping concentration. In addition, in consideration of the importance of heat treatment after epitaxial process, various heat treatments were conducted in order to know whether the above equation (b) was satisfied before starting the device process.
As a result, it has been recognized that the predetermined nitrogen and oxygen concentration need to be doped simultaneously in the silicon wafer, and that when an epitaxial wafer treated from the wafer is heat-treated under a predetermined high temperature condition, the epitaxial wafer can exhibit the excellent IG capability before starting the device process.
The present invention has been completed based on the above knowledge and views, and provides a method of manufacturing a silicon epitaxial wafer with the following manufacturing steps: producing a silicon single crystal having a nitrogen concentration of at least 1xc3x971012 atoms/cm3 and an oxygen concentration in a range of 10-18xc3x971017 atoms/cm3 (old ASTM), slicing a silicon wafer from said silicon single crystal, growing an epitaxial film on the surface of said silicon wafer, and conducting an annealing so as to satisfy the following equation (a), which is conducted at a temperature in a range of 800-1,100xc2x0 C. after growing said epitaxial film,
txe2x89xa733xe2x88x92((Txe2x88x92800)/100)xe2x80x83xe2x80x83(a)
wherein T(xc2x0 C.) is temperature, and t(hr) is time.